The present invention relates to a programmable semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit device which includes within its circuit wiring, wiring for programming and a laser masking pattern for realizing high productivity without requiring a high precision in laser irradiation for the programming.
An integrated circuit chip already manufactured can be programmed by disconnecting or short-circuiting parts of the wiring of the integrated circuit. This programming method has heretofore been used for, e.g., the programming of a read-only memory (ROM). In addition, it is recently utilized for the repair of defective cells in a memory device. These prior-art measures have usually employed the following expedients:
(1) A fuse is blown out by current, thereby to cut a wiring lead. PA1 (2) Energy is externally applied optically by laser pulses, thereby to cut or connect a wiring lead. PA1 (1) The energy of the laser needs to be high. Moreover, during the cutting, material 6 in or around the molten and scattered wiring part damages the nearby passivation film 4 as illustrated in FIG. 1(b), or the laser beam 5 is prone to damage the substrate near by. Therefore, the layout requires a sufficient margin and results in a large area. PA1 (2) Even with the large area, a satisfactorily high positional accuracy such as .+-.1 .mu.m for a 3 .mu.m pattern is needed for preventing any influence on the surrounding part in the case of the laser irradiation of the part to-be-cut. In order to perform processing at high speed for mass production, it is required of the processing apparatus to simultaneously meet the mutually contradictory specifications of high speed and high accuracy. Even when such a processing apparatus can be realized, it becomes very expensive. Moreover, from the standpoint of reliability, it is difficult to locate a function element around the part to-be-cut. PA1 (3) It is insufficient to use only the expedient of cutting. The use of short-circuiting is sometimes advantageous on the occupying area of a chip. PA1 (1) The laser irradiation is liable to damage the nearby substrate. Therefore, the layout requires a sufficient margin and results in a large area. PA1 (2) Even with the large area, a satisfactorily high positional accuracy is needed for suppressing influence on the surrounding part in the case of the laser irradiation of the part to-be-connected. In order to perform processing at high speed in the case of mass production, a processing apparatus becomes considerably expensive. Moreover, locating a function element around the part to-be-connected is difficult from the standpoint of reliability. PA1 (3) It is insufficient to use only the procedure of connection. The combined use with cutting is sometimes advantageous on the occupying area of a chip.
FIGS. 1(a) and 1(b) show an example of the prior art. It is a programming method wherein a wiring lead 3 of polycrystalline Si or Al which is electrically insulated from an Si substrate 1 by an SiO.sub.2 film 2 is cut by irradiating it with a laser beam 5 through an overlying passivation film 4. As an example of this method, R. P. Cenker et al. (1979 ISSCC Digest of Technical Papers) have reported the result of an experiment in which the wiring of decoders in a MOS memory was so altered that the defective cells of the memory connected to the decoders were separated and replaced with non-defective cells connected to dummy decoders.
However, the method in which the elements are disconnected in this manner has the following disadvantages:
FIGS. 2(a) and 2(b) show another example of the prior art. There has been proposed the technique wherein a high-resistivity polycrystalline Si wiring lead (resistance .apprxeq.10.sup.9 .OMEGA.)3b, which is electrically insulated from an Si substrate 1 by an SiO.sub.2 film 2 and which is held between low-resistivity polycrystalline Si wiring leads 3a, is irradiated with a laser 5 through an overlying passivation film 4 and thus turned into low resistivity and connected as illustrated in FIG. 2(b).
However, the method in which the wiring leads are connected in this manner has the following disadvantages:
FIGS. 3(a) to 3(c) are views illustrating a problem in the case where a function element is arranged around the wiring lead to be cut or connected in the prior art. FIG. 3(a) is a plan view, and FIGS. 3(b) and 3(c) are views of section A-B and section C-D in FIG. 3(a), respectively. Numeral 7 indicates PSG (phosphosilicate glass), numeral 8 Si.sub.3 N.sub.4 (silicon nitride), numeral 11 a first layer of Al wiring, and numeral 12 a second layer of Al wiring.
A Poly-Si (polycrystalline silicon) or Al wiring lead 3d, which is disposed on an Si substrate 1 with an SiO.sub.2 film 2 intervening therebetween, is irradiated with a laser 5 from above the Si substrate 1, to cut the Poly-Si or Al wiring lead 3d or to connect the Poly-Si wiring lead 3d. Since, however, a processing apparatus bears a heavy burden when positioning the laser beam to the wiring part of 2-3 .mu.m at high precision and performing processing at high speed, the size of the laser 5 to irradiate the wiring lead 3d is considerably larger than that of the wiring lead 3d in practical use. Then, in case of this prior-art example, function parts 16 located on both the sides of the wiring lead 3d are partly irradiated with the laser beam, and function parts 15 may be thermally affected. Therefore, in order to realize fast processing at the sacrifice of some precision, the function parts must be spaced sufficiently from the laser irradiation part to avoid damage. This inevitably makes the area of a chip large.